Phase locked loops (PLLs) can provide precise generation and alignment of timing for a wide variety of applications, such as for clock generation or clock data recovery. Digital phase-locked loops (DPLLs) are a viable alternative to traditional PLLs, in which a digital loop filter can be utilized to replace analog components. For example, all-digital phase locked loops (ADPLLs) are designed to utilize digital techniques throughout and can comprise a phase frequency detector, a loop filter, an oscillator, and a frequency divider. ADPLLs, as with other DPLLs, utilize a high-frequency clock source because they do not provide a true frequency synthesis. The oscillator is thus an important component involved in tuning the DPLL, which can involve coarse tuning and fine tuning operations.
The frequency of the signal output by the oscillator is adjusted by one or more tuning capacitor arrays such as one array for open loop band adjustment and another array for closed loop tuning. For example, coarse tuning (e.g., tuning a capacitor array for a band adjustment) can be implemented with a capacitor that is controlled by a binary coding, in which the coarse tuning process selects a frequency band. During the locking operation phase for a target frequency of operation and after coarse tuning, the coarse tuning is kept constant and the frequency resolution of the phase locked loop is enhanced with a fine tuning operation (e.g., setting a fine tuning field for locking the phase locked loop) in order to compensate for the error in the coarse tuning and to lock the oscillator at the target frequency.